Summarizing the ARM for x86 Programmers

I Am, Therefore I Think

RISC: The ARM architecture is RISC -based, yielding two facts of life: an instruction set that’s easy to decode, at the cost of memory accesses that aren’t atomic. While Intel’s more complex x86 architecture lets the programmer increment a memory location with a single machine instruction, ARM requires three explicit steps instead: load-to-register, increment-register, store-from-register. The load-store approach puts the burden on the programmer, rather than the CPU, to accomplish the same result, but the power savings is why ARM is the CPU of choice for battery-powered embedded devices like cell phones.

Predication: ARM instructions typically contain “1110” (hex E) in their highest bits, meaning the instructions always execute, but other combinations of high bits indicate conditional execution. For example, high bits of “0000” mean an instruction will execute only if the Zero flag is set, if for example a downward counter just reached zero, or a comparison between two…

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